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december 2010 doc id 17892 rev 1 1/21 21 L6391 high-voltage high and low side driver features high voltage rail up to 600 v dv/dt immunity 50 v/nsec in full temperature range driver current capability: ? 290 ma source, ? 430 ma sink switching times 75/35 nsec rise/fall with 1 nf load 3.3 v, 5 v ttl/cmos inputs with hysteresis integrated bootstrap diode comparator for fault protections smart shut-down function adjustable dead-time interlocking function compact and simplified layout bill of material reduction effective fault protection flexible, easy and fast design applications motor driver for home appliances, factory automation, industrial drives and fans. hid ballasts, power supply units. description the L6391 is a high-voltage device manufactured with the bcd ?off-line? tech nology. it is a single chip half-bridge gate driver for n-channel power mosfet or igbt. the high side (floating) section is designed to stand a voltage rail up to 600 v. the logic inputs are cmos/ttl compatible down to 3.3 v for easy interfacing microcontroller/dsp. an integrated comparator is available for protections against overcurrent, overtemperature, etc. table 1. device summary order codes package packaging L6391n dip-14 tube L6391d so-14 tube L6391dtr so-14 tape and reel www.st.com www.datasheet.net/ datasheet pdf - http://www..co.kr/
contents L6391 2/21 doc id 17892 rev 1 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 smart shut down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.1 cboot selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 block diagram doc id 17892 rev 1 3/21 1 block diagram figure 1. block diagram 56 $% 4%#4)/. ,%6%, 3()&4%2 "//4342!0$2)6%2 3 6 ## ,6' $2)6%2 (). ,). (6' $2)6%2 (6' /54 ,6 ' "//4 56 $%4%#4)/. '.$ 3$/$ $4 $%!$ 4)-% 2 ,/')# 3(//4 4(2/5'( 02%6%.4)/. &,/!4).'3425#452% #/-0!2!4/2 #0 from,6' 6## 6 6 #0 3-!24 3$ !-v www.datasheet.net/ datasheet pdf - http://www..co.kr/
pin connection L6391 4/21 doc id 17892 rev 1 2 pin connection figure 2. pin connection (top view) table 2. pin description pin n # pin name type function 1 lin i low side driver logic input (active low) 2 sd /od (1) i/o shut down logic input (active low)/open drain comparator output 3 hin i high side driver logic input (active high) 4 vcc p lower section supply voltage 5 dt i dead time setting 6 nc not connected 7 gnd p ground 8 cp- i comparator negative input 9 cp+ i comparator positive input 10 lvg (1) 1. the circuit guarantees less than 1 v on the lv g and hvg pins (@ isink = 10 ma), with v cc > 3 v. this allows omitting the ?bleeder? resistor connected bet ween the gate and the source of the external mosfet normally used to hold the pin low; the gate driv er assures low impedance also in sd condition. o low side driver output 11 nc not connected 12 out p high side (floating) common voltage 13 hvg (1) o high side driver output 14 boot p bootstrapped supply voltage 7$$ )*/ -*/ 4%0% /$ 065 )7( #005 (/% %5 $1 -7( $1 /$ !-v www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 truth table doc id 17892 rev 1 5/21 3 truth table note: x: don't care table 3. truth table input output sd lin hin lvg hvg lxxll hhl l l hlhll hllhl hhhlh www.datasheet.net/ datasheet pdf - http://www..co.kr/
electrical data L6391 6/21 doc id 17892 rev 1 4 electrical data 4.1 absolute maximum ratings note: esd immunity for pins 12, 13 and 14 is guaranteed up to 1 kv (human body model) 4.2 thermal data table 4. absolute maximum rating symbol parameter value unit min max v cc supply voltage -0.3 21 v v out output voltage v boot - 21 v boot + 0.3 v v boot bootstrap voltage -0.3 620 v v hvg high side gate output voltage v out - 0.3 v boot + 0.3 v v lvg low side gate output voltage -0.3 v cc + 0.3 v v cp- comparator negative input voltage -0.3 v cc + 0.3 v v cp+ comparator positive input voltage -0.3 v cc + 0.3 v v i logic input voltage -0.3 15 v v od open drain voltage -0.3 15 v dv out /dt allowed output slew rate 50 v/ns p tot total power dissipation (ta = 25 c) 800 mw t j junction temperature 150 c t stg storage temperature -50 150 c table 5. thermal data symbol parameter so-14 dip-14 unit r th(ja) thermal resistance junction to ambient 165 100 c/w www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 electrical data doc id 17892 rev 1 7/21 4.3 recommended operating conditions table 6. recommended operating conditions symbol pin parameter test condition min max unit v cc 4 supply voltage 12.5 20 v v bo (1) 1. v bo = v boot - v out 14-12 floating supply voltage 12.4 20 v v out 12 dc output voltage - 9 (2) 2. lvg off. vcc = 12.5 v logic is operational if v boot > 5 v 580 v v cp- 8 comparator negative input voltage v cp+ [ 2.5 v v cc (3) 3. at least one of the comparator's input mu st be lower than 2.5 v to guarantee proper operation. v v cp+ 9 comparator positive input voltage v cp- [ 2.5 v v cc (3) v f sw switching frequency hvg, lvg load c l = 1 nf 800 khz t j junction temperature -40 125 c www.datasheet.net/ datasheet pdf - http://www..co.kr/
electrical characteristics L6391 8/21 doc id 17892 rev 1 5 electrical characteristics 5.1 ac operation table 7. ac operation electrical characteristics (v cc = 15 v; t j = +25 c) symbol pin parameter test condition min typ max unit t on 1 vs 10 3 vs 13 high/low side driver turn-on propagation delay v out = 0 v v boot = vcc c l = 1 nf v i = 0 to 3.3 v see figure 3. 50 125 200 ns t off high/low side driver turn-off propagation delay 50 125 200 ns t sd 2 vs 10, 13 shutdown to high/low side driver propagation delay 50 125 200 ns t isd comparator triggering to high/low side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cp+; cp-=0.5 v 200 250 ns mt delay matching, hs and ls turn-on/off 30 ns dt 5 dead time setting range (1) r dt = 0 , c l = 1 nf 0.1 0.18 0.25 s r dt = 37k , c l = 1 nf, c dt = 100 nf 0.48 0.6 0.72 s r dt = 136k , c l = 1 nf, c dt = 100 nf 1.35 1.6 1.85 s r dt = 260k , c l = 1 nf, c dt = 100 nf 2.6 3.0 3.4 s mdt matching dead time (2) r dt = 0 , c l = 1 nf 80 ns r dt = 37k , c l = 1 nf, c dt = 100 nf 120 ns r dt = 136k , c l = 1 nf, c dt = 100 nf 250 ns r dt = 260k , c l = 1 nf, c dt = 100 nf 400 ns t r 10,13 rise time c l = 1 nf 75 120 ns t f fall time c l = 1 nf 35 70 ns 1. see figure 4 on page 9 2. mdt = | dt lh - dt hl | see figure 5 on page 12 www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 electrical characteristics doc id 17892 rev 1 9/21 figure 3. timing figure 4. typical dead time vs. dt resistor value hin hvg 50% 10% 90% 50% t r t f t on t off 90% 10% lin lvg 50% 10% 90% 50% t r t f t on t off 90% 10% lvg/hvg sd 90% 50% t f t sd 10% 5gwn2kp '7xv ? $ssur[lpdwhgirupxodiru 5gwfdofxodwlrqw\s 5gw>n @ a'7>?v@ www.datasheet.net/ datasheet pdf - http://www..co.kr/
electrical characteristics L6391 10/21 doc id 17892 rev 1 5.2 dc operation table 8. dc operation electrical characteristics (v cc = 15 v; t j = + 25 c) symbol pin parameter test condition min typ max unit v cc_hys 4 v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 9.5 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ; cp+=gnd; cp-=5 v 100 150 a i qcc quiescent current v cc = 15 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ; cp+=gnd; cp-=5 v 500 1000 a bootstrapped supply voltage section (1) v bo_hys 14-12 v bo uv hysteresis 1.2 1.5 1.8 v v bo_thon v bo uv turn on threshold 10.6 11.5 12.4 v v bo_thoff v bo uv turn off threshold 9.1 10 10.9 v i qbou undervoltage v bo quiescent current v bo = 9 v sd = 5 v; lin and hin = 5 v; r dt = 0 ; cp+=gnd; cp-=5 v 70 110 a i qbo v bo quiescent current v bo = 15 v sd = 5 v; lin and hin = 5 v; r dt = 0 ; cp+=gnd; cp-=5 v 200 a i lk high voltage leakage current v hvg = v out = v boot = 600 v 10 a r ds(on) bootstrap driver on resistance (2) lvg on 120 driving buffers section i so 10, 13 high/low side source short circuit current v in = v ih (t p < 10 s) 200 290 ma i si high/low side sink short circuit current v in = v il (t p < 10 s) 250 430 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 electrical characteristics doc id 17892 rev 1 11/21 logic inputs v il 1, 2, 3 low logic level voltage 0.8 v v ih high logic level voltage 2.25 v v il_s 1, 3 single input voltage lin and hin connected together and floating 0.8 v i hinh 3 hin logic ?1? input bias current hin = 15 v 110 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linl 1 lin logic ?0? input bias current lin = 0 v 3 6 20 a i linh lin logic ?1? input bias current lin = 15 v 1 a i sdh 2 sd logic ?1? input bias current sd = 15 v 10 40 100 a i sdl sd logic ?0? input bias current sd = 0 v 1 a 1. v bo = v boot - v out 2. r dson is tested in the following way: r dson = [(v cc - v cboot1 ) - (v cc - v cboot2 )] / [i 1 (v cc ,v cboot1 ) - i 2 (v cc ,v cboot2 )] where i 1 is pin 14 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 . table 8. dc operation electrical characteristics (v cc = 15 v; t j = + 25 c) (continued) symbol pin parameter test condition min typ max unit table 9. sense comparator (v cc = 15 v, t j = +25 c) symbol pin parameter test conditions min typ max unit v io 8, 9 input offset voltage -15 15 mv i ib 8, 9 input bias current v cp+ = 1 v, v cp- = 0.5 v 1 a v ol 2 open drain low level output voltage i od = - 3 ma v cp +=1v; v cp -=0.5v; 0.5 v t d_comp comparator delay r pull =100 k to 5 v on sd /od pin; v cp -=0.5v; voltage step on cp+ = 0 3.3v, 90 130 ns sr 2 slew rate c l = 180 pf; r pu = 5 k 60 v/ s www.datasheet.net/ datasheet pdf - http://www..co.kr/
waveforms definitions L6391 12/21 doc id 17892 rev 1 6 waveforms definitions figure 5. dead time and interlocking waveforms definitions lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving (*) hin and lin can be connected togheter and driven by just one control signal interlocking interlocking g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 smart shut down function doc id 17892 rev 1 13/21 7 smart shut down function L6391 integrates a comparator committed to the fault sensing function. the comparator input can be connected to an external shunt resistor in order to implement a simple over- current detection function. the output signal of the comparator is fed to an integrated mosfet with the open drain output available on pin 2, shared with the sd input. when the comparator triggers, the device is set in shut down state and both its outputs are set to low level leaving the half- bridge in tri-state. figure 6. smart shut down timing waveforms hin/lin hvg/lvg sd/od open drain gate (internal) upper threshold lower threshold cp- cp+ protection fast shut down: the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reach the lower input threshold real disable time 2 1 1 2 = (r on_od // r sd ) c sd = r sd c sd sd/od from/to controller v bias smart sd logic c sd r sd r on_od shut down circuit time constants www.datasheet.net/ datasheet pdf - http://www..co.kr/
smart shut down function L6391 14/21 doc id 17892 rev 1 in common over-current protection architectu res the comparator output is usually connected to the sd input and an rc network is connected to this sd /od line in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. differently from the common fault detection systems, L6391 smart shut down architecture allows to immediately turn-off the outputs gate driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual outputs switch-off. in fact the time delay between the fault and the outputs turn off is no more dependent on the rc value of the external network connected to the pin. in the smart shut down circuitry, the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. at the same time the internal logic turns on the open drain output and holds it on until the sd voltage goes below the sd logic input lower threshold. the smart shut down system provides the possibility to increase the time constant of the external rc network (that is the disable time after the fault event) up to very large values without increasing the delay time of the protection. any external signal provided to the sd pin is not latched and can be used as control signal in order to perform, for instance, pwm chopping through this pin. in fact when a pwm signal is applied to the sd input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa. www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 typical application diagram doc id 17892 rev 1 15/21 8 typical application diagram figure 7. application diagram 67 %&5&$5*0/ -&7&- 4)*'5&3 #005453"1%3*7&3 4 7 $$ -7( %3*7&3 )*/ -*/ )7( %3*7&3 )7( 065 -7( #005 67 %&5&$5*0/ (/% 4%0% %5 %&"% 5*.& 3 -0(*$ 4)005 5)306() 13&7&/5*0/ '-0"5*/(4536$563& $0.1"3"503 $1 gspn-7( 7$$ 7 7 $1 )7 50-0"% $cppu 7 #*"4 7 $$ '30.$0/530--&3 '30.$0/530--&3 '30.50 $0/530--&3 7 #*"4 4."35 4% !-v www.datasheet.net/ datasheet pdf - http://www..co.kr/
bootstrap driver L6391 16/21 doc id 17892 rev 1 9 bootstrap driver a bootstrap circuitry is needed to supply the hi gh voltage section. this function is normally accomplished by a high voltage fast recovery diode ( figure 8 ). in the L6391 a patented integrated structure replaces the external diode. it is realized by a high voltage dmos, driven synchronously with the low side driver (lvg), with diode in series, as shown in figure 9 . an internal charge pump ( figure 9 ) provides the dmos driving voltage. 9.1 c boot selection and charging to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge: equation 1 the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss. it has to be: equation 2 c boot >>> c ext e.g.: if q gate is 30 nc and v gate is 10 v, c ext is 3 nf. with c boot = 100 nf the drop would be 300 mv. if hvg has to be supplied for a long time, the c boot selection has to take into account also the leakage and quiescent losses. e.g.: hvg steady state consumption is lower than 200 a, so if hvg t on is 5 ms, c boot has to supply 1 c to c ext . this charge on a 1 f capacitor means a voltage drop of 1v. the internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 120 ). at low frequency this drop can be neglected. anyway increasing the frequency it must be taken in to account. c ext q gate v gate ------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 bootstrap driver doc id 17892 rev 1 17/21 the following equation is useful to compute the drop on the bootstrap dmos: equation 3 where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos and t charge is the charging time of the bootstrap capacitor. for example: using a power mos with a total gate charge of 30nc the drop on the bootstrap dmos is about 1 v, if the t charge is 5 s. in fact: equation 4 v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn?t allo w a sufficient charging time, an external diode can be used. figure 8. bootstrap driver with high voltage fast recovery diode figure 9. bootstrap driver with internal charge pump v drop i ch e arg r dson v drop q gate t ch e arg ------------------ r dson == v drop 30nc 5 s -------------- - 120 0.7v ? = to load h.v. hvg lvg c boot d boot boot v cc out b hvg lvg to load h.v. c boot v cc out boot www.datasheet.net/ datasheet pdf - http://www..co.kr/
package mechanical data L6391 18/21 doc id 17892 rev 1 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark. figure 10. package dimensions table 10. dip-14 mechanical data dim. mm. inch min typ max min typ max a1 0.51 0.020 b 1.39 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 2.54 0.050 0.100 www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 package mechanical data doc id 17892 rev 1 19/21 figure 11. package dimensions table 11. so-14 mechanical data dim. mm. inch min typ max min typ max a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 8.55 8.75 0.336 0.344 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.68 0.026 s 8 (max.) www.datasheet.net/ datasheet pdf - http://www..co.kr/
revision history L6391 20/21 doc id 17892 rev 1 11 revision history table 12. document revision history date revision changes 14-dec-2010 1 first release www.datasheet.net/ datasheet pdf - http://www..co.kr/
L6391 doc id 17892 rev 1 21/21 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com www.datasheet.net/ datasheet pdf - http://www..co.kr/

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